1. Field of the Invention
The present invention relates to a level shift circuit and, in particular, to a level shift circuit suitable for an integrated circuit device of an ECL-CMOS configuration.
2. Description of the Related Art
Of semiconductor IC devices, a bipolar complementary MOS (Bi-CMOS) structure is known generally as one of hybrid LSI's of analog/digital functions.
In an IC device of a Bi-CMOS configuration, an ECL-CMOS level shift circuit is sometimes inserted, for example, between an ECL (Emitter-Coupled-Logic) and a circuit of a CMOS configuration.
The level shift circuit is of such a type that, when an ECL signal cannot be input directly to the circuit of a CMOS configuration, the level shift circuit shifts that signal level to a predetermined level. In the level shift circuit, an emitter follower transistor for output is normally connected to a multi-input differential stage so that it operates at a non-saturated region.
The level shift circuit normally comprises a differential pair-transistor circuit section, an output transistor circuit section driven upon receipt of a drive signal from the differential pair-transistor circuit to shift that input signal level to a predetermined level, and so on.
In order to decrease a transmission delay time in the level shift circuit and achieve a high-speed processing throughout the whole circuit, a high-speed switching operation has to be achieved at the output transistor. Such a technique is performed normally by decreasing a capacitance of an output transistor, or the size of elements formed over a semiconductor substrate, and increasing a current by which the output transistor is driven. However, a decrease in capacitance of the output transistor results in a decreased output current capability of the level shift circuit. In order to increase a drive current of the output transistor, the output current of the differential pair transistor circuit can be increased, but it is necessary to increase a current by which the differential pair transistor circuit is driven.
In order to enhance an output current capability while maintaining a high-speed processing, it will be necessary to increase the size of the output transistor and hence to increase its drive current which is supplied as an output current from the differential-pair transistor circuit.
Further, the increase in the drive current and hence the output current results in an increase in dissipation power throughout the whole circuit and hence in quantity of heat evolved in the circuit itself. On the other hand, a decrease in dissipation current (dissipation power) of the circuit is required from another aspect to achieve a higher integration density or higher microminiaturization for a semiconductor circuit. If a low dissipation power circuit is to be achieved by decreasing the drive current and output current of each element, the transistor in the circuit as set out above is delayed in switching operation, involving a longer signal transmission delay time and decreasing an output current capability of the level shift circuit.
Even if the coming of an input signal is awaited at a standby time, a standby current needs to be flowed so as to effect a high-speed switching operation in the level shift circuit. If, in this case, such a standby current is to be decreased so as to decrease a dissipation current, then the output transistor becomes slower in switching operation to adversely affect a high/low (H/L) level difference.